1. Field of the Invention
The present invention generally relates to an interface controller, a method for controlling the interface controller, and a computer system, and more particularly relates to an interface controller which controls read request and read response carried out between a host apparatus and memory, a method for controlling the interface controller, and a computer system including the interface controller.
2. Related Art
As an interface used to connect a host apparatus (for example, CPU (Central Processing Unit), and a device (for example, memory), there is known the PCI Express (refer to Japanese Patent Laid-Open Publication No. 2005-322308).
At a time of memory read access from a CPU to a memory, a PCI Express interface controller sends to an interface controller of the memory, a packet (hereinafter referred to as “read request packet”) for requesting memory read, issued by the CPU, and then receives a packet (hereinafter referred to as “read response packet”) including read response data from the memory. In this case, the PCI Express interface controller saves the read response data into a receive buffer and at the same time, performs error check, and if there is no error, outputs response data to a system bus.
However, since read request is continuously issued by the CPU, when the size of read response data from the memory exceeds the storage capacity of the receive buffer, the receive buffer of the interface controller overflows and thus the performance of the interface controller lowers.
To address the above problem, as a technique of improving the performance of the interface controller, there is a method by which the CPU issues read request in view of the size of the receive buffer. In this case, in order to prevent overflow in the receive buffer, the CPU calculates the data size at a time of memory read access based on a side band signal indicating the size, the status, and the like of the receive buffer, and thereby controls the data size.
However, the processing of calculating the data size causes the performance of the CPU to lower. Further, a leased bus used to transmit a side band signal is needed, so the versatility of the whole system lowers.
PCI Express has an advantage by which the device can send back read response divided into multiple packets with respect to each read request. The number of packet divisions is determined by address and data length, and the presence/absence of division depends on the device.
However, since the host apparatus does not perceive the number of packet divisions for each read request, even when the CPU issues read request in view of the size of the receive buffer, when the number of packet divisions for each read request is large, the receive buffer overflows.